With the increase of circuits' functions, an IC requires more and more pins to implement various functions. For allowing fewer pins of an IC to implement more functions, many techniques that integrate multiple functions by a single pin of the IC have been proposed. A power good signal is an output signal of an IC that is popularly used for a system to identify whether the IC is ready for normal operation. Conventionally, a power good output function of an IC is implemented by means of an open drain or open collector structure, and the power good outputs of all the ICs in a system are connected together with a wire-or configuration. There is a pull-up resistor at the system side that is connected to the power good outputs of all the ICs in the system. When the power good outputs of all the ICs are open circuit, a power good signal will be triggered to notice the system that all the ICs are ready. If any of the power good outputs of all the ICs is short circuit to ground, no power good signals will be triggered, so the system learns that there is one or more ICs not ready yet.
As shown in FIG. 1, a conventional power converter includes an IC 10 for switching power switches M1 and M2 to convert an input voltage Vin into an output voltage Vout. The IC 10 has a multi-functional pin POK/EN for chip enable and power good control. FIG. 2 shows a circuit for the IC 10 to implement chip enable and power good control by the multi-functional pin POK/EN. Outside the IC 10, a pull-up resistor Rpull is connected between a supply voltage terminal VSB and the multi-functional pin POK/EN, and a switch SW1 is connected between the multi-functional pin POK/EN and a ground terminal GND and controlled by an enable signal EN. Inside the IC 10, a diode D2 and a switch SW2 are serially connected between the multi-functional pin POK/EN and the ground terminal GND, a comparator 12 compares the voltage at the multi-functional pin POK/EN with a threshold Vth1 to trigger a chip enable signal CE for enabling or disabling the IC 10, and a comparator 14 compares the voltage at a feedback pin FB of the IC 10 with a threshold Vth2 to trigger a power good signal PG for controlling the switch SW2. When the switch SW1 is closed circuit by the enable signal EN, the voltage at the multi-functional pin POK/EN is pulled down to the ground voltage, so the output signal CE of the comparator 12 will be logical low and thus disables the IC 10. When the switch SW1 is open circuit, the current Iok of the pull-up resistor Rpull will flow through the multi-functional pin POK/EN, the diode D2 and the switch SW2 to the ground terminal GND. Since the switch SW2, when being closed circuit, has a very small voltage drop thereacross, the diode D2 is required to have a forward bias VF large enough for the voltage at the multi-functional pin POK/EN to be higher than the threshold Vth1 so as to make the output signal CE of the comparator 12 be logical high to enable the IC 10. After the IC 10 is enabled, when the voltage at the feedback pin FB becomes higher than the threshold Vth2, indicating that the IC 10 is ready, the comparator 14 will remain the switch SW2 be open circuit. When all the ICs in a system are ready, the voltage at the multi-functional pin POK/EN will be pulled up and then a power good signal will be triggered to inform the system that all the ICs are ready.
The chip enable control and the power good control follow respective standards. Generally, the comparator 12 will trigger a chip enable signal CE for enabling the IC 10 when the voltage at the multi-functional pin POK/EN becomes higher than 0.3V, and a power good condition will be identified when the voltage at the multi-functional pin POK/EN is higher than 0.4V or 0.8V. However, the difference between 0.3V and 0.4V or 0.8V is very small and thus, due to variations of the process, voltage and temperature, it is likely that the voltage at the multi-functional pin POK/EN becomes higher than 0.4V or 0.8V before the IC 10 is really ready, thereby leading to inaccurate power good detection by the system. In addition, the resistance of the pull-up resistor Rpull also affects the voltage at the multi-functional pin POK/EN. If the pull-up resistor Rpull has a small resistance, the generated current Iok is relatively large. As a feature of a diode, the larger the current of the diode D2 is, the higher its forward bias VF is. Thus, the resistance of the pull-up resistor Rpull can not be too small; otherwise the voltage at the multi-functional pin POK/EN may incorrectly trigger a power good signal before the IC 10 is really ready. However, if the pull-up resistor Rpull has an excessively large resistance, the current Iok will be very small and thus the voltage at the multi-functional pin POK/EN will increase slowly, meaning that it will take more time to trigger a power good signal. Particularly, the more are the ICs of a system that are connected together, the slower will be the response of the entire system. In addition, in such a structure as shown in FIG. 2, since the current Iok is limited within a small range, for example 50 μA, if the diode D2 is stronger, the voltage at the multi-functional pin POK/EN may fail to be higher than the threshold Vth1, causing that the IC 10 is unable to be enabled. On the contrary, if the diode D2 is weaker, a power good signal may be incorrectly triggered before the IC 10 is ready. As discussed above, many limitations existing in the conventional circuit for implementing chip enable and power good control by a single pin of an IC make the circuit design be difficult.